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Altera_Forum's avatar
Altera_Forum
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15 years ago

Seperate PLL power planes for Cyclone III devices?

I have a question about PLL power supply.

In "Cyclone III Device Family Pin Connection Guidelines", Altera requires a totally seperated VCCA & VCCD power island for Cyclone III PLLs.

But when I check their cycloneIII_3c25_dsk reference design, I found they simply connect the VCCA & VCCD pins to 2.5V & 1.2V supply, without any "islands".

This really confusd me. And I felt it's really ugly that there is five power supply (1.2v, 2.5v, 3.3v, 1.2v_pll, 2.5v_pll) to drive cyclone iii chips.

How did you guys do when you design PCBs with Cyclone III chips on a 4or6 layer board? Thanks for any advise.

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    This question has been addressed elsewhere in the forum so you might try a search. The decision of whether or not you need to decouple the VCCA and VCCD pins from the other power supplies really depends on your design. Which device are you using? How many PLLs are you going to use? What frequencies are you going to run at?

    Most likely you can get away without the separate power islands. At the very least you could probably just filter the main supplies to provide VCCA and VCCD. But again this depends on your design.

    FvM might have a more in-depth response on this one.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thank you very much.

    Could you give me some tips or keywords to search in this forum? I found FvM post a lot.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I read the posts about vcca & vccd of PLL in this forum yesterday and it seems that this is not a simple "yes or no" question and depends on the design requirements. As FvM said, the most important factor is the clock "jitter".

    Particularly for my design, only one chips connected to this FPGA is 66MHz*16bits synchronous interface while all others are asynchronous, can I just tie vcca to 2.5V and vccd to 1.2V power supply?

    (My opinion is "Yes":) )

    Thank you two very much.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Yes, I will use two PLLs: one for this 66MHz (in source synchronous mode) and the other for something else logic ( 20MHz input, 20M/40M/50M/100M outputs) used only inside the FPGA.

    Is there anything I should take care of?

    Thanks again.