Forum Discussion
Altera_Forum
Honored Contributor
15 years agoI read the posts about vcca & vccd of PLL in this forum yesterday and it seems that this is not a simple "yes or no" question and depends on the design requirements. As FvM said, the most important factor is the clock "jitter".
Particularly for my design, only one chips connected to this FPGA is 66MHz*16bits synchronous interface while all others are asynchronous, can I just tie vcca to 2.5V and vccd to 1.2V power supply? (My opinion is "Yes":) ) Thank you two very much.