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Altera_Forum
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12 years ago

Self clocking FPGA?

We have a need to power down large parts of our design - including the clock source for the device - but keep portions of the FPGA (Cyclone III, EP3C25) running. There are no other clock sources fed ...
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Altera_Forum
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12 years ago

Hi FvM,

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I experienced that the minimal VCO frequency can be much lower than the specified value, beyond a reasonable range.

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Could you clarify this comment.

I interpret it to mean that you have observed the output frequency of an unlocked PLL to be much lower than the data sheet stated minimum end of the lock range of the PLL.

Did you happen to observe this on a Cyclone III?

Personally using an unlocked VCO is not something I would normally advocate, as it involves using the device in an unspecified manner, i.e., Murphy's Law all but guarantees that this scheme will work on the first 10 prototype boards, but then not work for the production run!

Cheers,

Dave