Self clocking FPGA?

Another random idea ...

A PLL will output a clock regardless of whether is has an input clock or not. The VCO will sit at either the high-end or low-end of its tuning range. You could configure PLL from your external clock source, and look at the output frequency when its locked versus unlocked. Perhaps you could use the "locked" output to decide if the external clock is valid, and if its not, reset your logic, but keep a small amount of logic alive, being clocked from the unlocked PLL clock output. Worst-case if the "normal" output frequency is too high, you could use another PLL output with a larger divider and clock your low-power logic from that.

Cheers,

Dave