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Dave - the majority of the power that we are trying to save is in the external ECL logic that provides the high precision vernier and buffering of clocks to the rest of the system - including the FPGA. Shutting this off is an easy way for us to save much more power than all of the power that the FPGA consumes, but then we have the problem of needing a secondary clock source since we have just taken away the primary FPGA clock.
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Ah, that makes sense. Thanks for clarifying.
Its good to hear ECL is not dead yet :)
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The ALTINT_OSC megafunction (which appears to be just a call to cycloneiii_oscillator) WORKS great! Just tie the
oscena to logic high, and you have a clock. I do not know the exact frequency, but it initially appears to be >= 50mhz.
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Its possible that the AS configuration clock (DCLK output) is half this. The DCLK typical frequency is 33MHz, so perhaps the oscillator is 66MHz.
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My first experiment was to attach the altint_osc to a PLL, but that didn't work - some sort of fabric interconnect problem.
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Bummer. Try routing it to a clock mux and see if that works. The output of the clock mux can go to a PLL.
Cheers,
Dave
Honored Contributor
