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Thanks Dave - but this design is in production and we are not going to change the PCB for this "feature".
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The PLL, multiple resets, and clock multiplexer options most likely do not require a board change, so any of those options can be tested.
I'm interested in whether Daixiwen's suggestion works too. However, even with that option, you still need to figure out a low power clocking scheme. I believe the configuration clock is 33MHz (typical), so that clock may still be too fast for "low power". A PLL clock from your existing clock source, generating multiple outputs, including a low-frequency clock, with control logic that disables the clock to the higher powered logic will likely be your best bet, since this disables the clock tree to that logic (least power).
Cheers,
Dave
Honored Contributor
