Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSelf clocking FPGA?
We have a need to power down large parts of our design - including the clock source for the device - but keep portions of the FPGA (Cyclone III, EP3C25) running. There are no other clock sources fed ...
Altera_ForumHonored Contributor
Honored ContributorThe configuration clock isn't always disabled after configuration, you can use it through the ALTINT_OSC megafunction (in the I/O category). It's not documented though, AFAIK.
