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Altera_Forum
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12 years ago

Self clocking FPGA?

We have a need to power down large parts of our design - including the clock source for the device - but keep portions of the FPGA (Cyclone III, EP3C25) running. There are no other clock sources fed ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The configuration clock isn't always disabled after configuration, you can use it through the ALTINT_OSC megafunction (in the I/O category). It's not documented though, AFAIK.