Self clocking FPGA?

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Does anyone have any novel ideas as to how to create a clock using just FPGA resources?

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You could create an RC oscillator using logic, however, at that point you are leaving yourself open to PVT (process-voltage-temperature) variations.

I'd recommend deciding "how low power" you need to go, and then just design your system to achieve that level of power down. For example, if you really want low-power, turn your FPGA off, and use a microcontroller to decide when to turn back on :) Obviously suggestions like this are highly design-dependent. FPGAs have high static power. Before getting too fancy with your clocking logic, you need to determine whether you will actually save enough power.

Power saving ideas;

1. Have two external clocks; one for your always on logic and another for your logic that you want to stop clocking.

2. Use multiple resets; one for your always on logic, and another for the logic that you want to stop toggling.

3. Use a PLL.

You could have your always on logic clocked at a low frequency, or change to a low frequency when you want low-power mode. Your other logic could have its clock disabled.

(1) will have a slight power advantage because by disabling the clock external to the FPGA, you are stopping the clock tree from toggling. You can achieve the same thing using a clock multiplexer (if the Cyclone III supports it); one input would be the clock, the other would be a grounded clock pin.

All of these ideas should be easy to test using an evaluation board (most have current-sense for the core logic).

Personally, if I want low-power, an FPGA is not the first thing that comes to mind :)

Cheers,

Dave