Searchable registers

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If I create a bank of D flip flops in a design. How do I go about making that register have an address that is consistant? In a nutshell If I want to create a registers FFAD or any name how do I create it with D flipflops and ensure that every time I compile my design I create that register?

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I'm not sure what you are asking.

Lets say I want to create an Avalon-MM slave block of registers. I start with my control_register component, instantiate several of those along with an address decoder, and then add an Avalon-MM slave interface. I then create a _hw.tcl file so that SOPC Builder will recognize it.

The SOPC system is then used to define the base address of that block of control registers.

Is this the type of thing you are asking a question about?

Cheers,

Dave

Dave,

Thanks for the reply. I'm asking about plain old VHDL registers. I need to query some input pins and store that data in a register that another can go look at. If I just park it in a block of D flip flops how is anyone going to know where to find the data whereas if I somehow had an address assigned to the register I could then find it and aquire the data.

Thanks

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Thanks for the reply. I'm asking about plain old VHDL registers. I need to query some input pins and store that data in a register that another can go look at. If I just park it in a block of D flip flops how is anyone going to know where to find the data whereas if I somehow had an address assigned to the register I could then find it and aquire the data.

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Your response is still not very clear.

If I have a signal on some pins that I register, then the register signal has a name, eg., pio. If I want to 'read' that pio signal, I can route the pio bus through components via a port. I can route pio to the Avalon-MM slave registers I mentioned above and make the state of the pins visible at some decoded address, i.e., a read-only register. This would allow software to read the state of the pins. If you want hardware to read the state of the pins, you just route the pio signal to the components that need it.

Cheers,

Dave

I'm not following what you are asking for either but what you describe sounds like a memory to me.

What do you mean by this: "that another can go look at" (another what?)

What i understand is a simple addressable register....

reg [15:0] FFAD;

always @(posedge clk)

if (addr == 3 && ctrl)

FFAD <= inp;

this register FFAD has a consistent address every time you compile. Do you mean something like that

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That might work. Would you suggest a certain type of memory that comes with a Megafunction that is easy to use?

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Look at the altsyncram component.

However, it would be worthwhile if you could explain what you are trying to do. There are many people on this list who can offer advice. However, your current description is pretty vague.

You say you want to look at the state of some pins? But what are you looking for, a state change, or the current value? If you want to capture the pin state when anything changes, you could write a small state machine to detect the change and write a timestamp and the pins to a register, and then generate an interrupt. If you were going to get lots of these events, then you could use a RAM or FIFO instead of a register, so that you could capture multiple events.

Cheers,

Dave

Okay. Here is goes. And thanks again for all those who strive to answer questions. I have a cyclone III that will be accessed by a stratix further on down the line via some sort of opcode. I need the stratix to be able to access the registers within the cyclone III to retrive certain information.

Hope that helps

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I have a cyclone III that will be accessed by a stratix further on down the line via some sort of opcode. I need the stratix to be able to access the registers within the cyclone III to retrive certain information.

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Why does it need to be an opcode?

The typical way to implement this is to have a bus protocol between the FPGAs.

For example, see this photo;

http://www.ovro.caltech.edu/~dwh/carma_board/

The PowerPC connects to the system controller FPGA (the one right next to it), and then the system controller FPGA connects to four data processing FPGAs and a couple of MAX II CPLDs. As far as the PowerPC is concerned, its all one big address map.

How many signals to you have between your Cyclone and Stratix?

Cheers,

Dave