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Altera_Forum
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14 years ago

SDRAM setup violation when reading

Hi, I am using a Cyclone 4 FPGA running at 100Mhz. My design has a SDRAM interface also running at 100Mhz. Currently the PLL is generating 1 clock, which is used to clock the SDRAM...
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Altera_Forum
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14 years ago

Altddio for the clock? It can make a slight difference, but it's not significant.

Clocking on the falling edge is the same thing as shifting 180 degrees, just saves a clock tree. But if they're available, shifting gives you more granularity. Just be sure to note where you might need a multicycle.