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Honored Contributor
Honored ContributorSDRAM read out of sync
I am testing SDRAM read and write using nios. I wrote a simple function with loops to write to 15 memory locations and read them back. for(i=min; i<max; i++) {
IOWR(SDRAM_BASE,0,i...
Altera_ForumHonored Contributor
Honored ContributorWhat is the contents of your pbase table? You need different addresses for each entry if you want to be sure to read back the same values. Besides The Nios 2 CPU is not capable of doing a non-aligned 32-bit transfer. That means that when you use an address that is not aligned (such as 1,2 or 3) you will in fact always read/write at the aligned address (0 in that case).
