based on my experiences i would recommend to use a pll with 2 outputs set both outputs to the same frequency. for example set c0 to 96MHz and c1 also to 96MHz. connect c0 to fpga internal ips like nios and connect c1 to an external pin, a dedicated clock output pin, and let this pin be sdram clock.
now you can, and must, set the phase of c1 that is done by calculation as described in one of the appnotes.
for these calculations you need a couple of values. some values are coming from your sdram datasheet and you can directly use them. the other values are comming from your first compilation. i would recommend if you use the classic timing analyser to set it up to give slow and fast timings seperatly.
now it gets a bit anoying
have a look at the timing folder and look for tco th .. values.
you should mark all those signals that are sdram related (A[..] DQ[] as well as the control signals) and search for the related min and max values you need for calculation.
now enter all these values into a spread sheet that does the calculation for you and you get the phase shift.
now modify your pll by using the calculated value and rebuild the system.
it is very importand that you check the timing tco th ... values that they do not change too much.
but some side notes.
these calculation do not take into account that there is another component between the fpga and your sdram, thats your pcb.
i use a very fast scope and compare the timing relation ship between sdram clk and RAS to see if it as it should be.
also i would recommend to remeasuhe again at your lowest and your highest operating temperature.
this is important due to the therma behavioral, even hold timing for example gets critical under lower temperatur as the fpga gets faster.
next thing is to setup quartus correctly. use fast input output registers and setup the current correctly to avoid over and undershots.
the higher you get with sdrqam clock the more importat this gets.
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