Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

SDRAM on DE0-nano board

Hi, I am still not having any success writing and reading from the SDRAM on on the DE0-nano board from the FPGA. I have built a system in qsys which includes a Nios II and SDRAM controller an...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

--- Quote Start ---

Look at the top-level code again - there is no ADC component instantiated.

I have not used the ADC on the DE0-nano. Its an SPI device, so its pretty easy to write a controller from scratch.

The type of controller you write depends on what you want to do with it, for example,

1. Use an existing "SPI Master Controller" and write software to interface to the ADC.

2. Create an Avalon-MM slave with 8 addresses, and when you access any one of these 8 addresses perform a conversion. Use a DMA controller to transfer blocks of samples to SDRAM.

3. Create an Avalon-MM ADC controller interface, where you set the ADC clock frequency, and the rate at which it auto-reads channels. Software then just reads the last conversion value from 8 registers.

Cheers,

Dave

--- Quote End ---

Hi Dave, thanks a lot for your reply, I would have a look on the three options you stated here and see what I should do next, thanks again for your inputs!