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Altera_Forum
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12 years ago

SDRAM on DE0-nano board

Hi, I am still not having any success writing and reading from the SDRAM on on the DE0-nano board from the FPGA. I have built a system in qsys which includes a Nios II and SDRAM controller an...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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I have tested the example in the zip file and and it works fine, so there should be no problem with the hardware.

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Great! Its always useful to have minimal designs that prove your hardware works.

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Going back to the SDRAM controller in Qsys, I have changed the refresh rate and power-on delay as you said but there is still something wrong.

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In what respect? What error are you seeing?

What you have done seems reasonable. The Qsys system inserts width adapters, so the fact that your JTAG master is 32-bits and your SDRAM interface is 16-bits should not matter.

Whenever I see a problem in hardware, I first look at the problem using the Signal Tap II logic analyzer (which you can add to your FPGA design), and then I use a simulation to duplicate what I see in the hardware.

Try those tools and see how far you get. Ask questions when you get stuck.

Cheers,

Dave