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I have tested the example in the zip file and and it works fine, so there should be no problem with the hardware.
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Great! Its always useful to have minimal designs that prove your hardware works.
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Going back to the SDRAM controller in Qsys, I have changed the refresh rate and power-on delay as you said but there is still something wrong.
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In what respect? What error are you seeing?
What you have done seems reasonable. The Qsys system inserts width adapters, so the fact that your JTAG master is 32-bits and your SDRAM interface is 16-bits should not matter.
Whenever I see a problem in hardware, I first look at the problem using the Signal Tap II logic analyzer (which you can add to your FPGA design), and then I use a simulation to duplicate what I see in the hardware.
Try those tools and see how far you get. Ask questions when you get stuck.
Cheers,
Dave
Honored Contributor
