SDRAM on DE0-nano board

Hi Dave,

I have tested the example in the zip file and and it works fine, so there should be no problem with the hardware.

Going back to the SDRAM controller in Qsys, I have changed the refresh rate and power-on delay as you said but there is still something wrong.

Again, I am not sure if my settings in the memory profile tab are correct for the SDRAM on the DE0-nano. I have the data width set to 16 bits , chip select :1 , banks: 4 Under address width , Row : 13 and Column : 9.

The address assigned to the SDRAM controller is 0x10000000, therefore I have added the following to the tcl script. I am not sure if this is correct as I more or less replicated how you wrote it for the on-chip SRAM and changed the base address from 0x1000 to 0x10000000. The on-chip RAM also has a 32-bit data width instead of 16-bit so I'm wondering if my below code is acceptable? : Thanks

proc sdram_write {offset data} {
    global jtag
    if {!} {
        jtag_open
    }
    set addr 
    master_write_32 $jtag(master) $addr $data
    return
}
proc sdram_read {offset} {
    global jtag
    if {!} {
        jtag_open
    }
    set addr 
    return 
}