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I have now added an SDRAM controller to the qsys design from the jtag-to-avalon-mm example, gave it address 0x0 and assigned all the appropriate pins for the DE0-nano SDRAM with pin-planner.
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But the SDRAM controller that Altera provides *DOES NOT* also come with timing constraints. Did you add them?
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When I then try to write from the tcl console with command "sdram_write 0 0x12345" for example and read it back with "sdram_read 0" , I am only reading 0x00000045, hence only the lower 8 bits seem to be written everytime. What would be the issue here. Is it something with the tcl script or my SDRAM controller settings?
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Most likely SDRAM controller settings, though you could have a board or pin assignments error where the data mask bit for one lane is bad and is masking that byte lane.
Regarding the SDRAM controller settings, I recall changing the refresh rate to 7.8125us (half the default) and the power-on init delay to 200us (twice the default), to match the settings used in a couple of DE0-nano examples that I looked at.
Try the zip file I provided you, I know it works on my DE0-nano, so if it does not work on yours, that implies a hardware error where the mask bit is stuck.
Cheers,
Dave
Honored Contributor
