SDRAM on DE0-nano board

Hi Dave,

I have now added an SDRAM controller to the qsys design from the jtag-to-avalon-mm example, gave it address 0x0 and assigned all the appropriate pins for the DE0-nano SDRAM with pin-planner.

In the jtag_cmds_sc.tcl script , I have added extra code to "talk" to the external SDRAM on the DE0-nano as follows :

proc sdram_write {offset data} {
	global jtag
	if {!} {
		jtag_open
	}
	set addr 
	master_write_32 $jtag(master) $addr $data
	return
}
proc sdram_read {offset} {
	global jtag
	if {!} {
		jtag_open
	}
	set addr 
	return 
}

When I then try to write from the tcl console with command "sdram_write 0 0x12345" for example and read it back with "sdram_read 0" , I am only reading 0x00000045, hence only the lower 8 bits seem to be written everytime. What would be the issue here. Is it something with the tcl script or my SDRAM controller settings?

In my SDRAM controller settings , the data width is set to 16 bits , chip select :1 , banks: 4 Under address width , Row : 13 , Column : 9

Thanks,

Paul