Altera_Forum
Honored Contributor
Honored ContributorSDRAM Controller SDC Constraints
When using SDRAM Controller are SDC Constraints relative to SDRAM needed? Thank you
Forum Discussion
Altera_ForumHonored Contributor
Honored ContributorYeah, unfortunately the Altera SDRAM controller does not seem to create timing constraints like the DDR2/DDR3 IP core does.
I wrote some constraints for the DE0-nano SDRAM that are also valid for the SDRAM used on some of the other Terasic DE-series boards. See the example design and SDC file posted in this thread; http://www.alteraforum.com/forum/showthread.php?t=45927 Cheers, Dave
