SDRAM Controller SDC Constraints

Question

When using SDRAM Controller are SDC Constraints relative to SDRAM needed?  Thank you

altera_forum · Answer

Yeah, unfortunately the Altera SDRAM controller does not seem to create timing constraints like the DDR2/DDR3 IP core does.

I wrote some constraints for the DE0-nano SDRAM that are also valid for the SDRAM used on some of the other Terasic DE-series boards.

See the example design and SDC file posted in this thread;

Cheers,

Dave

altera_forum · Answer

Thank you very much for the example. Altera should document better their ip-core.

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