Forum Discussion
MFric2
New Contributor
New ContributorSDR SDRAM Controller MAX II
Hey guys, iam trying to Interface an SDR SDRAM from Micron with a MAX II CPLD. Iam able to read between 10 - 400 Adresses but then i think because of timing issues the Read fails... Because iam us...
NurAida_A_Intel
Frequent Contributor
Frequent ContributorHi Sir,
You can try to constraint the output clock from the FPGA using generated clock constraint as explain in this link:
Hope this is helpful.
Thanks.
Regards,
NAli1
