SDC syntax for declaring generated clocks

To do a divide by n, you create a signal that pulses every nth clock cycle (the signal is asserted for one full clock cycle out of every n clock cycles). That signal is used as the clock enable. The registers running at the slower speed with that enable are clocked by the full-speed clock signal; the enable gives the same effect as using a slower clock. You can use multicycle exceptions in TimeQuest to say that any path between clock-enabled registers is allowed n clock cycles for setup.

The Quartus II version 7.1 handbook shows how to describe the clock enable in HDL. Volume 1, Section II, Chapter 6, Example 6-31 has a VHDL example with a clock enable together with other control signals that you can omit if you don't need them. You need the nested "if" that describes the enable inside the "if" that detects the clock edge.

Here's an example of a way to create the multicycle exceptions for a divide by n (set to divide by 4 in the example). This example uses get_fanouts to apply a single pair of setup and hold exceptions to all paths where the source and destination registers both use the same clock enable. The set_multicycle_path -from and -to fields each contain the full set of registers using the clock enable. TimeQuest will apply the multicycle exceptions to all the paths that actually exist between all possible pairings of these registers. When you use the clock enable resource in silicon, it is OK if the new data actually arrives at the destination sooner than the n clock cycles. The multicycle hold of n-1 tells TimeQuest that the old data does not have to be held during the clock cycles when the clock enable is deasserted.

set all_enabled_registers ]
set clock_enable_divide_by_n 4
set_multicycle_path -setup $clock_enable_divide_by_n -from $all_enabled_registers -to $all_enabled_registers
set_multicycle_path -hold  -from $all_enabled_registers -to $all_enabled_registers