SDC syntax for declaring generated clocks

Hi Brad,

Thanks for your reply. I have checked your post. But i have some problems. I cannot use PLL's. I just have a clock and i need to divide this directly. Now, how can i use a clock enable to get a divide by 1 or 2 or n clock , with approx 50% duty cycle.

if this not possible. Let me know, how i can assign this divided clock to a global assignment. Because this doesn't exist on my top level entity for the FPGA.

Regards,

Anil.