Forum Discussion

Honored Contributor

18 years ago

SDC syntax for declaring generated clocks

Hello, Below, I have pasted a module that i have created. Now, i want to declare the outputs of this module as clocks in the SDC constraint file. entity CLKCTRL is Port ( -- Clo...

Altera_Forum

Honored Contributor

18 years ago

Be careful about driving clocks with logic resources. Something like a clock divider is better done with a PLL if you have a PLL available or with a clock enable.

I have a post at http://www.alteraforum.com/forum/showthread.php?t=453&highlight=clock+enable with some considerations if you do use logic resources to do the clock division.

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SDC syntax for declaring generated clocks

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