Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSDC syntax for declaring generated clocks
Hello, Below, I have pasted a module that i have created. Now, i want to declare the outputs of this module as clocks in the SDC constraint file. entity CLKCTRL is Port ( -- Clo...
Altera_ForumHonored Contributor
Honored ContributorBe careful about driving clocks with logic resources. Something like a clock divider is better done with a PLL if you have a PLL available or with a clock enable.
I have a post at http://www.alteraforum.com/forum/showthread.php?t=453&highlight=clock+enable with some considerations if you do use logic resources to do the clock division.
