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Honored Contributor
Honored ContributorSDC for ALTCLKCTRL
Hello, I have an ALTCLKCTRL component implemented in my design targeting a Cyclone V FPGA. The ALTCLKCTRL has 4 of its inputs occupied: 1. Clock_1 driven by an FPGA pin. 2. Clock_2 dri...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- You definitely have to manually constrain this --- Quote End --- So you disagree with what I wrote in# 10 ? You assume it's a bug in the tool ?
