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Altera_Forum
Honored Contributor
9 years agoSDC for ALTCLKCTRL
Hello, I have an ALTCLKCTRL component implemented in my design targeting a Cyclone V FPGA. The ALTCLKCTRL has 4 of its inputs occupied: 1. Clock_1 driven by an FPGA pin. 2. Clock_2 dri...
Altera_Forum
Honored Contributor
9 years agoYou definitely have to manually constrain this. You need to find the output of the altclkctrl in the node finder, and then do:
create_generated_clock -name pin1 -source [get_ports pin1] {altclkctrl|dout} create_generated_clock -name pin2 -source [get_ports pin2] {altclkctrl|dout} -add create_generated_clock -name pll_clk_1 -source [get_pins altpll...clkout1] {altclkctrl|dout} -add create_generated_clock -name pll_clk_2 -source [get_pins altpll...clkout2] {altclkctrl|dout} -add The last item is the name of the altclkctrl. The -source for the pins is just the name of the top-level port, while the -source for the PLL can be found when you run Report Clocks and is the Target column for the PLL generated clock. For the -name option, naturally name then whatever you want. Then you'll need something like: set_clock_groups -exclusive -group {pin1} -group {pin2} -group {pll_clk_1} -group {pll_clk_2} Naturally, add other clocks to this command as appropriate.