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Altera_Forum
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9 years ago

SDC for ALTCLKCTRL

Hello, I have an ALTCLKCTRL component implemented in my design targeting a Cyclone V FPGA. The ALTCLKCTRL has 4 of its inputs occupied: 1. Clock_1 driven by an FPGA pin. 2. Clock_2 dri...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

That sounds right. The key is what you see in the unconstrained paths report. If it's not there, it's not an issue. But you should still have set_clock_groups for the output of the mux.