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Honored Contributor
Honored ContributorSDC for ALTCLKCTRL
Hello, I have an ALTCLKCTRL component implemented in my design targeting a Cyclone V FPGA. The ALTCLKCTRL has 4 of its inputs occupied: 1. Clock_1 driven by an FPGA pin. 2. Clock_2 dri...
Altera_ForumHonored Contributor
Honored ContributorExcluding a bug - the only explanation I can think of is this:
For timing purposes, the tool doesn't treat the output of ALTCLKCTRL as a clock source. Instead, it views it ALTCLKCTRL as a balanced delay in the clock path for all MUX inputs. I.E: nothing more than a "long wire" leading to the input of the global clock tree. Therefore, it's never considered as an additional clock source. Do you agree with this assumption ?
