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Honored Contributor
Honored ContributorSDC for ALTCLKCTRL
Hello, I have an ALTCLKCTRL component implemented in my design targeting a Cyclone V FPGA. The ALTCLKCTRL has 4 of its inputs occupied: 1. Clock_1 driven by an FPGA pin. 2. Clock_2 dri...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Not exactly and that's where it gets strange... In the "Clock Status Summary" it doesn't show at all (not even as a red unconstrained path). I don't see in the "Clock Tree" report either. All other clocks are there, the output of ALTCLKCTRL isn't... But despite the phantom behavior the MUX and the design it drives work. --- Quote End --- you will find all details here: https://www.mixdown.ca/redmine/attachments/download/71/timing_analysis_of_internally_generated_clocks_in_timequest_v2.0.pdf figure 19 (not really figure but SDC
