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Altera_Forum
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9 years ago

SDC for ALTCLKCTRL

Hello, I have an ALTCLKCTRL component implemented in my design targeting a Cyclone V FPGA. The ALTCLKCTRL has 4 of its inputs occupied: 1. Clock_1 driven by an FPGA pin. 2. Clock_2 dri...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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Clock creation is for creating essentially reference points for timing analysis, not defining delays.

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Exactly. If I don't use the "create_generated_clock" command on the output of ALTCLKCTRL - how would the tool know that it should analyze timing in reference to that point ?

I mean, we use the "create_generated_clock" on all PLL outputs - so why is the ALTCLKCTRL any different ? Why doesn't it deserve a "create_generated_clock" command on it's output ?