Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSDC for ALTCLKCTRL
Hello, I have an ALTCLKCTRL component implemented in my design targeting a Cyclone V FPGA. The ALTCLKCTRL has 4 of its inputs occupied: 1. Clock_1 driven by an FPGA pin. 2. Clock_2 dri...
Altera_ForumHonored Contributor
Honored ContributorIt does have delay, but you don't need to define the delay since the tool knows about internal resource delays. Clock creation is for creating essentially reference points for timing analysis, not defining delays. You can define delays if you want, but it's not necessary for internal paths. Using set_clock_groups will tell TimeQuest that only one clock is active at a time, the way your design is supposed to work.
