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Altera_Forum
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9 years ago

SDC for ALTCLKCTRL

Hello, I have an ALTCLKCTRL component implemented in my design targeting a Cyclone V FPGA. The ALTCLKCTRL has 4 of its inputs occupied: 1. Clock_1 driven by an FPGA pin. 2. Clock_2 dri...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Suppose only one of the clocks is active at a given time.

Why "set_clock_groups" is enough ? Shouldn't I also apply the "create_generated_clock" for the ALTCLKCTRL's output ?

Surely the ALTCLKCTRL component has some delay from input to output.