SDC constraints for DE Boards Audio Codec WM8731

OK i see. The WM8731 is supplying the clock. I thought the FPGA was doing that.

In that case, you basically have to constrain a source synchronous interface (SDR). In the datasheet the data looks to be center aligned relative to Bclk. So we have to use virtual clock to account for this.

# real clock

create_clock -name bclk -period 325 [get_ports BCLK]

# virtual clock

create_clock -name bclk_launch -period 325 -waveform {162.5 325}

# shift the rising and falling edges by 162.5 ns

# then relative to bclk_launch

set_input_delay -clock bclk_launch -max 15 [get_ports ADCDAT]

set_input_delay -clock bclk_launch -min 0 [get_ports ADCDAT]

set_output_delay -clock bclk_launch -max 10 [get_ports DACDAT]

set_output_delay -clock bclk_launch -min -10 [get_ports DACDAT]

I'm not sure if this will work, give it a try.