SDC constraints for DE Boards Audio Codec WM8731

Bigger image of timing diagram: http://it.tinypic.com/r/9foftf/8

WM8731 datasheet (pag. 14) say that DACDAT (generated from FPGA) should be have setup and hold relations with BCLK generated from WM8731.

BCLK is not generated by me but is an output of audio codec.

I have a 50 MHz clock that go up to 100 MHz and clock NIOS system. A phase corrected -3ns clock at 100 MHz is generated for SDRAM.

Another 50 MHz onboard clock goes up to 18.432 and feed XCK of WM8731.

I use university program audio ip that unfortunately comes without constraints.

WM8731 datasheet: http://www.cs.columbia.edu/~sedwards/classes/2008/4840/wolfson-wm8731-audio-codec.pdf

Why I need multicycle constraints?

Thanks