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Altera_Forum's avatar
Altera_Forum
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13 years ago

scfifo output latency

Hello,

May i know what is the output latency for the SCFIFO operating at normal mode and optimized for area?

Refering to the userguide date august 2012, the output latencies are the following:

wrreq/rdreq to full:1

wrreq/rdreq to empty:1

wrreq/rdreq to usedw[]:1

rdreq to q[]:1

I tried with a simple design using modelsim altera but the output latency for rdreq to full & rdreq to q[] obtained seems to be different from the userguide.

My results using modelsim are:

rdreq to q[]:0

rdreq to full:0[/B]

[/B]

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    May i know what is the output latency for the SCFIFO operating at normal mode and optimized for area?

    I tried with a simple design using modelsim altera but the output latency for rdreq to full & rdreq to q[] obtained seems to be different from the userguide.

    --- Quote End ---

    The user manual has errors. This attached simulation can be used to view the latencies. 

    
Procedure to run the FIFO simulations:
1. Unzip altera_fifos.zip
2. Start Modelsim and change directory to the altera_fifos folder
3. Source the simulation script, i.e., source scripts/sim.tcl
4. Run the single-clock FIFO simulation (sim_sc) or dual-clock FIFO simulations (sim_dc) with the desired options; showahead on/off, use EAB/LCs, and output register on/off

    Cheers,

    Dave