scfifo output latency

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May i know what is the output latency for the SCFIFO operating at normal mode and optimized for area?

I tried with a simple design using modelsim altera but the output latency for rdreq to full & rdreq to q[] obtained seems to be different from the userguide.

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The user manual has errors. This attached simulation can be used to view the latencies.

Procedure to run the FIFO simulations:
1. Unzip altera_fifos.zip
2. Start Modelsim and change directory to the altera_fifos folder
3. Source the simulation script, i.e., source scripts/sim.tcl
4. Run the single-clock FIFO simulation (sim_sc) or dual-clock FIFO simulations (sim_dc) with the desired options; showahead on/off, use EAB/LCs, and output register on/off

Cheers,

Dave