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Altera_Forum
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17 years ago

Scaling core clock of 100MHz to 23MHz & 20MHz

Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources ...
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Altera_Forum
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17 years ago

As far as I experienced, ModelSim simulation of LVDS receivers and DPA was almost matching the real chip behaviour.

I understand that you are particularly referring to the word boundary integrity problem discussed in the manual. To my opinion, the issue only occurs if the correct alignment position is near to the initial position. In this case, some channels may need zero alignment pulses and some channel would need -1 pulse. Cause no negative shift is possible, these channel's phase is advanced by n-1 bit positions (n is the deserialization factor), crossing the word boundary.

If the typical aligned phase is in the middle of DPA range, this never happens. So I don't think that it's necessary to check the word integrity in the DPA logic, which could be done e.g. by using a two word (alternating) train pattern.