sampled signal on falling or risins edge?

No the same rules apply when interfacing to an external component. The component has a setup and hold requirement on it's inputs. You must use these values in addition to your board trace delays to create timing constraints for your project. I have actually never used a falling clock edge to drive data out to an external component (except when creating DDR interfaces). There are occasions where it is appropriate. Those occasions are when all of the timing factors indicate a falling edge will give the best timing performance.

By using both edges for logic, you may actually be taking away from the timing margin. Essentially you are giving the fitter a tighter timing requirement that it has to work in. Yes you've made life easier for the fitter when it comes to meeting the hold requirement but you've made it twice as bad for setup. Here is the rule: always do everything on the same clock edge until you come across a very good reason not to. By that time you will have enough experience to know the difference.

Jake