sampled signal on falling or risins edge?

This is a common point of confusion for beginning logic designers. The questions at hand are not what edge to use for data sampling but instead are you meeting timing requirements. Every flip-flop has a setup and hold requirement. How long before the latching clock edge and how long after the clock edge must the data be present at the input of the flip-flop.

It is not typical in most designs to use both clock edges. The times for using both edges is when the behavior is an inherent part of the design itself (such as DDR interfaces).

Use the rising clock edge for both signals. The timing analyzer and fitter have the responsibility of determining whether or not the setup and hold times are being met. You can specify your temperature range in the project settings within Quartus II and the timing analyzer will take those settings into account.

Jake