sampled signal on falling or risins edge?

Hello,

Thank for you answer.

You can see these signal on attach file.

I don’t have problem on the design speed.

But though it was not sure sampled signal on rising edge if

it is generated on the previous rising edge. I ‘m anxious for metastability

problem: sampled signal when it change.

What do you think about that moreover if I test my fpga in incubator with a wide temperature range!