Forum Discussion

Occasional Contributor

4 years ago

RX clock out varying speed after Programming FPGA Multiple times

Hi, I am using Arria 10 GX dev kit , with transceivers in my design. I am working on 5G speed, data width is 40Bits. so my rx_clkout should be fixed 125Mhz. I am seeing a difference in rx_clko...

Kshitij_Intel

Frequent Contributor

4 years ago

Hi Rajesh,

This is not the expected Behavior, please check the rx_is_lockedtodata, rx_is_lockedtoref, signals.

Please go through the Intel® Arria® 10 Transceiver PHY User Guide

https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/transceiver-phy-overview.html

It has all the info you need. Please check reset sequence also. Follow Chapter 4.

Thank you

Kshitij Goel

Forum Discussion

RX clock out varying speed after Programming FPGA Multiple times

Please go through the Intel® Arria® 10 Transceiver PHY User Guide

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