Running Nios II on DDR2 (UNIPHY controller)

Check to make sure the byte enables are enabled in the Uniphy settings. I'm not sure when it happened but I noticed a few months ago they were disabled when I was using it in Qsys. CPUs don't always perform word accesses so you need those byte enables.

Also if you want any kind of performance from that CPU I would put it on the same clock domain as the SDRAM. Even if you have to decrease the SDRAM speed to achieve timing it'll still be much faster than the async. clock crossing SOPC Builder is inserting in your design (~9 extra clock cycles for every read with no back to back accesses)