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Altera_Forum
Honored Contributor
Honored ContributorRTL, Post synthesis and Gate Level Simulation
Hi. I can't find the clear differences on the topic above.
From what i understand, RTL : Functional simulation is working on any technolgy Post Synthesis: Functional Simulation on targeted device of specific technology Gate Level: Timing simulation that includes timing info after fitting process Am i right? Pls give clear differences between each another. Besides, in Simulating Designs with EDA Tools.pdf, it mentions abt Post Synthesis and gate level simulation. However, in quartus ii, i can't find the post synthesis simulation. Is the rtl simulation means post synthesis simulation? Any idea? thanks3 Replies
Altera_ForumHi, I'm having touble with the PowerPlay tool in Quartus II. I'm a beginner to this software. I have generated the reqd vwf , vcd and saf files but when i run the PowerPlaytool i keep getting an error saying ' Successful run of Assembler reqd' . I the run the fitter and assembler from the processing/start menu , but i still receive the same error. I would be greatful if you could help me .
Thank You.- Altera_Forum
RTL simulation is the simulation of the code pre-synthesis. Its like behavioural simulation. With good design practice 99 times out of 100 the RTL simulation should match the gate level simulation.
- Altera_Forum
all the answer can be found in Simulating Designs with EDA Tools.pdf. thanks
