RS232 ip core qsys

You just need a custom master that will read the status registers before performing data movements. This is necessary so that you don't inadvertingly over/underflow the FIFO TX and RX registers. So a simple state machine could do this.

Creating such a master would probably take a day to implement whereas using Nios II would take minutes to write the code since the driver is done for you and it would be more flexible too (error checking into the UART data stream for example would be dirt simple with Nios II).