RS232 convert Lower case to Upper case

Hi,

Really new to VHDL. I'm supposed to edit a code to convert lower case to upper case with a UART model.. can someone assist me. code is below..

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MP0_top is

port

(

sysclk : in std_logic; -- RAD system clock

RESET_low : in std_logic; -- Active low

FPGA_SERIAL1_TX : out std_logic;

FPGA_SERIAL1_RX : in std_logic

);

end MP0_top;

architecture rtl of MP0_top is

----------------------------------------------

-- Component declarations --

----------------------------------------------

component mmu_uart_top

port

(

Clk : in std_logic; -- main clock

Reset_n : in std_logic; -- main reset(phjones made active high)

TXD : out std_logic; -- RS232 TX data

RXD : in std_logic; -- RS232 RX data

ck_div : in std_logic_vector(15 downto 0);

-- clock divider value

-- used to get the baud rate

-- baud_rate = F(clk) / (ck_div * 3)

-- bus interface

CE_N : in std_logic; -- chip enable

WR_N : in std_logic; -- write enable

RD_N : in std_logic; -- read enable

A0 : in std_logic; -- 0 - Rx/TX data reg; 1 - status reg

D_IN : in std_logic_vector(7 downto 0);

D_OUT : out std_logic_vector(7 downto 0);

-- interrupt signals- same signals as the status register bits

RX_full : out std_logic;

TX_busy_n : out std_logic

);

end component;

----------------------------------------------

-- Signal declarations --

----------------------------------------------

signal reset : std_logic; -- Reset active high

signal WR_N : std_logic; -- Active low write enable

signal RD_N : std_logic; -- Active low read enable

signal TXD_temp : std_logic; -- Allow output of TXD to test pin

signal my_pulse : std_logic; -- Make sure load pulsed for 1 clk

signal D_IN : std_logic_vector(7 downto 0); -- Data to Transmit

signal D_OUT : std_logic_vector(7 downto 0); -- Data Recieved

signal RX_full : std_logic; -- Byte of Data to Ready to read

signal TX_busy_n : std_logic; -- Active low indicate busy transmitting

begin

-- Simple echo process

------------------------------------------------------------

------------------------------------------------------------

-- --

-- Process Name: Echo --

-- Description: Determine when an character arrives then --

-- transmit the character back to the sender --

-- --

------------------------------------------------------------

------------------------------------------------------------

Echo : process(sysclk)

begin

if (sysclk = '1' and sysclk'event) then

-- Defaults

RD_N <= '1';

WR_N <= '1';

my_pulse <= '0';

if(reset = '0') then

-- Check if a byte has arrived

if(RX_full = '1' and TX_busy_n = '1' and my_pulse = '0') then

my_pulse <= '1';

RD_N <= '0'; -- clear read full flag

end if;

----------------------------------

Only to modify this section......

if(RD_N = '0' and TX_busy_n = '1') then

WR_N <= '0'; -- start transmission

D_IN <= D_OUT;

end if;

------------------------------------------

end if;

end if;

end process Echo;

-- Combinational assignments

FPGA_SERIAL1_TX <= TXD_temp;

reset <= not RESET_low;

-- Port map UART

UART_1 : mmu_uart_top

port map

(

Clk => sysclk, -- main clock (33 MHz)

Reset_n => reset, -- main reset(phjones made active high)

TXD => TXD_temp, -- RS232 TX data

RXD => FPGA_SERIAL1_RX, -- RS232 RX data

ck_div => x"0478",

-- clock divider value

-- used to get the baud rate

-- baud_rate = F(clk) / (ck_div * 3)

-- bus interface

CE_N => '0', -- chip enable

WR_N => WR_N, -- write enable

RD_N => RD_N, -- read enable

A0 => '0', -- 0 - Rx/TX data reg; 1 - status reg

D_IN => D_IN, -- Data to send off-chip

D_OUT => D_OUT, -- Data recieved to the chip

-- interrupt signals- same signals as the status register bits

RX_full => RX_full,

TX_busy_n => TX_busy_n

);

end rtl;