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Honored Contributor
Honored ContributorRMII Mode Selection / Strapping CYCLONE III
Hi, I am working in ALTERA CYCLONE III . I have designed a module with the following NIOS II Processor + Custom Ethernet MAC working in RMII Mode + SSRAM. The Ethernet PHY used in this FPGA i...
Altera_ForumHonored Contributor
Honored ContributorBasically you can do it with a state machine. On a MII interface you transfer 4 bits on a 25MHz clock, whereas on an RMII interface you transfer 2 bits on a 50 MHz clock. You can put a state machine in the 50MHz clock domain that processes the high bits on every other cycle and the low bits on the next ones.
