RLDRAM II Simulation Issues

I generated a RLDRAM II controller in Quartus and now I'm verify the functionality. The status of the RLDRAM controller passed (local_init_done and local_int_success), but the mem_we_n appears 27.5 ns before the mem_dq. The mem_cs_n goes low with the mem_we_n, but the data (dq) does not line up.

Suggestions?