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Honored Contributorring oscillator as a clock
Hi,
I am having a problem using 2 ring oscillators as 2 different clocks to 2 8-bit counters. When I use them separately they are working. But when I combine the two circuits in one design the output of the two counters is (X). Please check the code and see the pic for more details.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
entity ring_slow_fast is
port(counter1, counter2: out std_logic_vector(7 downto 0);
reset_n: in std_logic; -- active-low asynchronous reset
clk_fast, clk_slow: out std_logic -- synthesized clock
);
end entity;
architecture beh of ring_slow_fast is
signal node2: std_logic_vector(1 to 3); -- Internal nodes.
signal node1: std_logic_vector(1 to 5);
signal cnt1 :std_logic_vector(7 downto 0);
signal cnt2 :std_logic_vector(7 downto 0);
signal clk_slow_sig : std_logic;
signal clk_fast_sig : std_logic;
attribute keep1: boolean;
attribute keep2: boolean;
attribute keep1 of node1: signal is true;
attribute keep2 of node2: signal is true;
begin
node1(1) <= node1(5) nand reset_n;
node1(2) <= not node1(1);
node1(3) <= not node1(2);
node1(4) <= not node1(3);
node1(5) <= not node1(4);
clk_slow_sig <= not node1(1);
clk_slow<=clk_slow_sig;
counter1_process :process(clk_slow_sig)
begin
if(clk_slow_sig'event and clk_slow_sig='1')then
cnt1<=cnt1+1;
end if;
counter1<=cnt1;
end process;
node2(1) <= node2(3) nand reset_n;
node2(2) <= not node2(1);
node2(3) <= not node2(2);
clk_fast_sig <= not node2(1);
clk_fast<=clk_fast_sig;
counter2_process :process(clk_fast_sig)
begin
if(clk_fast_sig'event and clk_fast_sig='1')then
cnt2<=cnt2+1;
end if;
counter2<=cnt2;
end process;
end architecture;
5 Replies
Altera_ForumYou are targeting generating clock from logic delays. While this is theoretically possible but practically FPGAs cannot generate useful clock like signals based on delays.
The practical approach is to to provide time base for fpga(reference clock) then either multiply/divide it in fpga PLLs or divide it in logic using simple counters or ring counters. ring counters are preferred for small counters as they are built from back to back registers and so pass timing readily. Thus your code will look like this:
clk_slow_sig <= node1(1);process(reset,clk) begin if reset = '1' then node1 <= "00001"; elsif rising_edge(clk) then node1 <= node1(4 downto 0) & node1(4); end if; end process;- Altera_Forum
I presume, it's a trivial timing failure.
You didn't tell about the involve FPGA family, but besides the problems addressed by kaz, it seems like the frequency of your ring oscillator is beyond feasible clock speeds. Timing closure for the counters has to be evaluated manually because the timing analyzer isn't prepared to determine the frequency of ring oscillators. - Altera_Forum
Thank u Kaz. It's working. :)))))
Fvm, u mentioned to the timing closure for the counter. would u PLEASE explain more. cause it is very important to me to understand this :) - Altera_Forum
In a design with a regular clock, Quartus timing analysis will check if all design part scan work with the respective clock frequency, e.g. the counter. The clock frequency information will be also used during synthesis and design fit.
The clock frequency of your ring oscillator isn't known and can't be considered by Quartus. A - Altera_Forum
Got it. Thanks a lot :)
