ring oscillator as a clock

You are targeting generating clock from logic delays. While this is theoretically possible but practically FPGAs cannot generate useful clock like signals based on delays.

The practical approach is to to provide time base for fpga(reference clock) then either multiply/divide it in fpga PLLs or divide it in logic using simple counters or ring counters.

ring counters are preferred for small counters as they are built from back to back registers and so pass timing readily.

Thus your code will look like this:

process(reset,clk)
begin
if reset = '1' then
    node1 <= "00001";
elsif rising_edge(clk) then
   node1 <= node1(4 downto 0) & node1(4);
end if;
end process;

clk_slow_sig <= node1(1);