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Altera_Forum's avatar
Altera_Forum
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12 years ago

Resistors on DE2 board switches

I have a question about the resistors which are connected from SW13 to SW17, but the SW0 to SW12 are directly connected to FPGA in DE2 board, like in DE2-70. Anybody knows why? In comparison, all switches from DE2-117 board are connected to FPGA with resistors.

Thanks in advance.

Edit:

I didn't realized that there are a category for DE2 boards in "University Program". Can a moderator move the post?

(Good start in the forums for me, :))

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    Anybody knows why? In comparison, all switches from DE2-117 board are connected to FPGA with resistors.

    --- Quote End ---

    My guess is that the resistors are there to "idiot proof" the design.

    If a switch is connected to 3.3V, and a user configures the FPGA with a design that accidentally drives a logic low on an FPGA pin configured to the switch, i.e., on a pin that should be configured as an input, then the series resistor will limit the current and save damaging the pin.

    Older versions of Quartus would unfortunately set unused pins to ground, so this problem was easy to create.

    Both versions of the DE2 board should have had these resistors on all pins that could be defined as I/O (the resistors would not be required on FPGA input-only pins).

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    My guess is that the resistors are there to "idiot proof" the design.

    If a switch is connected to 3.3V, and a user configures the FPGA with a design that accidentally drives a logic low on an FPGA pin configured to the switch, i.e., on a pin that should be configured as an input, then the series resistor will limit the current and save damaging the pin.

    Older versions of Quartus would unfortunately set unused pins to ground, so this problem was easy to create.

    Both versions of the DE2 board should have had these resistors on all pins that could be defined as I/O (the resistors would not be required on FPGA input-only pins).

    Cheers,

    Dave

    --- Quote End ---

    I didn't realized that SW0 to SW12 in DE2 board are connected to "dedicated clock input pins" from Cyclone II. Furthermore, with your explanation now I understand the design.

    Thank you!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    @banenky, Resistors directly connected with FPGAs are a common practice in FPGA board design. As DWH said, they are used to idiot proof the design in case the pin is operated at low level. Another explanation can be that even the pins are set as output pins, these resistors could be used as current limiting resistors for driving any sensitive ICs connected to the FPGA. Normally it isn't needed with the dedicated clock input pins but safety comes first. It's better to have them in your design rather than leaving them out.

    pcb assembly prototype (http://www.7pcb.ca/prototype-pcb-assembly/)