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SamWhite's avatar
SamWhite
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Resets being routed through CLKENA blocks and then not meeting Recovery timing

Arria 10 devices, Quartus Prime 19.1. We have a reset pipe module that is used to create a synchonised asynchronous reset. It was my understanding that the tool should then be easily able to meet tim...
Fpga Devkit
  • sstrell's avatar
    sstrell
    3 years ago

    It's entirely possible for a high fanout control signal put on a global routing channel to have timing issues. Nothing unusual about taking it off the global as a possible solution (which seemed to work in your case). If you do want to use a global, you still could but you may need to check which clock control block is being used and adjust other global signal use using assignments like you did. The "insertion delay", the delay caused by routing the signal over to an available clock control block to get it onto the global routing channel, is usually the culprit. If you're design is already using some CCBs, it may have forced the Fitter to select one farther away, causing the issue.

Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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